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VIV0005TFJ
(R)
C
S
US
C
NRTL
US
VTM DC to DC Voltage Transformer
TM
FEATURES
* 40 Vdc to 1 Vdc 130 A Voltage Transformer
- Operating from standard 48 V or 24 V PRM regulators
TM
* 150 A rated with reduced case temperature at 30C * High efficiency (>91%) reduces system power
consumption
* High density (117 A/in2) * "Full Chip" V* I Chip package enables surface mount,
low impedance interconnect to system board
* Contains built-in protection features:
Overvoltage Lockout Overcurrent Short Circuit Over Temperature
* Provides enable / disable control, internal temperature
monitoring, current monitoring
* ZVS / ZCS resonant Sine Amplitude Converter topology * Less than 50C temperature rise at full load
in typical applications TYPICAL APPLICATION
DESCRIPTION The V* I Chip Voltage Transformer is a high efficiency (>91%) Sine Amplitude Converter (SAC)TM operating from a 26 to 55 Vdc primary bus to deliver an isolated output. The Sine Amplitude Converter offers a low AC impedance beyond the bandwidth of most downstream regulators, which means that capacitance normally at the load can be located at the input to the Sine Amplitude Converter. Since the K factor of the VIV0005TFJ is 1/40, that capacitance value can be reduced by a factor of 1600, resulting in savings of board area, materials and total system cost. The VIV0005TFJ is provided in a V* I Chip package compatible with standard pick-and-place and surface mount assembly processes. The co-molded V*I Chip package provides enhanced thermal management due to large thermal interface area and superior thermal conductivity. With high conversion efficiency the VIV0005TFJ increases overall system efficiency and lowers operating costs compared to conventional approaches. The VIV0005TFJ enables the utilization of Factorized Power ArchitectureTM providing efficiency and size benefits by lowering conversion and distribution losses and promoting high density point of load conversion.
VIN = 26 to 55 V VOUT = 0.65 to 1.37 V(NO LOAD)
IOUT = 130 A(NOM) K = 1/40
* High End Computing Systems * Automated Test Equipment * High Density Power Supplies
PART NUMBER
VIV0005TFJ
DESCRIPTION
-40C to 125C TJ
Regulator
PR PC TM IL VC SG OS CD
Voltage Transformer
PC VC IM TM
PRM
+Out +In
VTM
+Out
+In
VIN
-In -Out -In -Out
L O A D
Factorized Power Architecture (See Application Note AN:024)
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 1 of 18
VIV0005TFJ
1.0 ABSOLUTE MAXIMUM VOLTAGE RATINGS
PRELIMINARY DATASHEET
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. MIN MAX UNIT MIN MAX UNIT + IN to - IN . . . . . . . . . . . . . . . . . . . . . . . PC to - IN . . . . . . . . . . . . . . . . . . . . . . . . TM to -IN . . . . . . . . . . . . . . . . . . . . . . . . VC to - IN . . . . . . . . . . . . . . . . . . . . . . . . -1 -0.3 -0.3 -0.3 60 20 7 20 VDC VDC VDC VDC IM to - IN................................................. + IN / - IN to + OUT / - OUT (hipot)........ + IN / - IN to + OUT / - OUT (working)... + OUT to - OUT....................................... -1 0 3.15 100 60 5.5 VDC VDC VDC VDC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40C < TJ < 125C (T-Grade); All other specifications are at TJ = 25C unless otherwise noted.
ATTRIBUTE Input Voltage Range VIN Slew Rate VIN UV Turn Off SYMBOL VIN dVIN /dt VIN_UV Module latched shutdown, No external VC applied, IOUT = 130A VIN = 40 V VIN = 26 V to 55 V VIN = 40 V, TC = 25C VIN = 26 V to 55 V, TC = 25C K = VOUT / VIN, IOUT = 0 A VOUT = VIN * K - IOUT * ROUT, Section 11 30C < Tc < 100C, IOUT_MAX = - (2/7) * Tc + 159 TC = 30C TPEAK <10 ms, IOUT_AVG 130 A IOUT_AVG 130 A VIN = 40 V, IOUT = 130 A VIN = 26 V to 55 V, IOUT = 130 A VIN = 40 V, IOUT = 65 A VIN = 40 V, IOUT = 150 A VIN = 40 V, Tc = 100C, IOUT = 130 A 26 A < IOUT < 130 A TC = -40C, IOUT = 130 A TC = 25C, IOUT = 130 A TC = 100C, IOUT = 130 A 18 2 3.2 CONDITIONS / NOTES No external VC applied VC applied MIN 26 0 TYP MAX 55 55 1 26 6.3 7.5 4.5 6 4 UNIT VDC V/s V
No Load Power Dissipation DC Input Current Transfer Ratio Output Voltage Output Current (Average) Output Current (Peak) Output Power (Average) Efficiency (Ambient)
PNL IIN_DC K VOUT IOUT_AVG IOUT_PK POUT_AVG
W A V/V V A A W %
1/40 130 150 195 178 87.5 81.7 89.1 86.2 85.1 78 0.45 0.55 0.7 1.53 3.06 89.2 91 88.2 87.5 0.575 0.668 0.82 1.61 3.22 125 150 360 0.75 0.87 1.02 1.67 3.34 150
AMB HOT 20%
ROUT_COLD ROUT_AMB ROUT_HOT FSW FSW_RP VOUT_PP LOUT_PAR COUT_INT
Efficiency (Hot) Efficiency (Over Load Range) Output Resistance (Cold) Output Resistance (Ambient) Output Resistance (Hot) Switching Frequency Output Ripple Frequency Output Voltage Ripple Output Inductance (Parasitic) Output Capacitance (Internal) PROTECTION OVLO Overvoltage Lockout Response Time Output Overcurrent Trip Short Circuit Protection Trip Current Output Overcurrent Response Time Constant Short Circuit Protection Response Time Thermal Shutdown Setpoint
% % m m m MHz MHz mV pH F
COUT = 0 F, IOUT = 130 A, VIN = 40 V, 20 MHz BW, Section 12 Frequency up to 30 MHz, Simulated J-lead model
VIN_OVLO+ TOVLO IOCP ISCP TOCP TSCP TJ_OTP
Module latched shutdown Effective internal RC filter
55.01
57.5 0.24
59.99
V s
165 275 Effective internal RC filter (Integrative). From detection to cessation of switching (Instantaneous) 125
200 7.13 2 130
275
A A ms s
135
C
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v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 2 of 18
VIV0005TFJ
3.0 SIGNAL CHARACTERISTICS
PRELIMINARY DATASHEET
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40C < TJ < 125C (T-Grade); All other specifications are at TJ = 25C unless otherwise noted.
VTM CONTROL : VC * PRM VC can be used as valid wake-up signal source. * VC voltage may be continuously applied; there will be no VC current drawn when VIN > 26 V. SYMBOL VVC_EXT IVC CONDITIONS / NOTES Required for startup, and operation below 26 V. See Section 7. VC = 11.5 V, VIN = 0 V VC = 11.5 V, VIN > 26 V Fault mode. VC > 11.5 V Required for proper startup; 0 C < TC < 100 C Required for proper startup; -40 C < TC < 100 C VC = 16.5 V, dVC/dt = 0.25 V/s VC = 11.5 V to PC high, VIN = 0 V, dVC/dt = 0.25 V/s VC = 0 V MIN 11.5 0 0.001 0.0025 100 0 60 TYP MAX UNIT 16.5 150 0 0.25 V/s 0.25 250 75 1 125 mA s F V mA
* Used to wake up powertrain circuit. * A minimum of 11.5 V must be applied indefinitely for VIN < 26 V to ensure normal operation. * VC slew rate must be within range for a succesful start. SIGNAL TYPE STATE ATTRIBUTE External VC Voltage Steady VC Current Draw ANALOG INPUT Start Up
VC Slew Rate VC Inrush Current VC to PC Delay
dVC/dt IINR_VC TVC_PC CVC_INT
Transitional
Internal VC Capacitance
PRIMARY CONTROL : PC * The PC pin enables and disables the VTM. * Module will shutdown when pulled low with an impedance When held below 2.0 V, the VTM will be disabled. less than 850 . * PC pin outputs 5 V during normal operation. PC pin is equal to 2.5 V * In an array of VTMs, connect PC pin to synchronize startup. during fault mode given VIN > 26 V and VC > 11.5 V. * PC pin can't sink current and will not disable other module * After successful start-up and under no fault condition, PC can be used as during fault mode. a 5 V regulated voltage source with a 2 mA maximum current. SIGNAL TYPE STATE Steady ATTRIBUTE PC Voltage PC Source Current PC Resistance (Internal) PC Source Current PC Capacitance (Internal) PC Resistance (External) PC Voltage PC Voltage (Disable) PC Pull Down Current PC Disable Time PC Fault Response Time SYMBOL VPC IPC_OP RPC_INT IPC_EN CPC_INT RPC_EXT VPC_EN VPC_DIS IPC_PD TPC_DIS_T TFR_PC Internal pull down resistor Section 7 60 2 5.1 From fault to PC = 2.0 V 5 100 2.5 CONDITIONS / NOTES MIN 4.7 50 50 TYP 5 150 100 MAX UNIT 5.3 2 400 300 1000 3 2 V mA k A pF k V V mA s s
ANALOG OUTPUT
Start Up Enable DIGITAL INPUT / OUPUT Disable Transitional
TEMPERATURE MONITOR : TM * The TM pin monitors the internal temperature of the VTM controller IC * The TM pin has a room temperature setpoint of 3 V within an accuracy of 5C. and approximate gain of 10 mV/C. * Can be used as a "Power Good" flag to verify that the VTM is operating. SIGNAL TYPE STATE ATTRIBUTE TM Voltage TM Source Current TM Gain TM Voltage Ripple Disable DIGITAL OUTPUT (FAULT FLAG) Transitional TM Voltage TM Resistance (Internal) TM Capacitance (External) TM Fault Response Time SYMBOL VTM_AMB ITM ATM VTM_PP VTM_DIS RTM_INT CTM_EXT TFR_TM CONDITIONS / NOTES TJ controller = 27C MIN 2.95 TYP 3 10 CTM = 0 F, VIN = 40 V, IOUT = 40 A Internal pull down resistor From fault to TM = 1.5 V 25 120 0 40 10 200 50 50 MAX UNIT 3.05 100 V A mV/C mV V k pF s
ANALOG OUTPUT
Steady
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Page 3 of 18
VIV0005TFJ
3.0 SIGNAL CHARACTERISTICS (CONT.)
PRELIMINARY DATASHEET
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40C < TJ < 125C (T-Grade); All other specifications are at TJ = 25C unless otherwise noted.
CURRENT MONITOR : IM * The IM pin voltage varies between 0.1 V and 1.825 V representing the output current within 25% under all operating line temperature conditions between 50% and 100%. SIGNAL TYPE STATE ATTRIBUTE IM Voltage (No Load) IM Voltage (50%) IM Voltage (Full Load) IM Gain IM Resistance (External) SYMBOL VIM_NL VIM_50% VIM_FL A IM RIM_EXT * The IM pin provides a DC analog voltage proportional to the output current of the VTM. CONDITIONS / NOTES TJ = 25C, VIN = 40 V, IOUT = 0 A TJ = 25C, VIN = 40 V, IOUT = 65 A TJ = 25C, VIN = 40 V, IOUT = 130 A TJ = 25C, VIN = 40 V, IOUT > 65 A MIN 0.1 TYP 0.206 0.857 1.825 14.9 MAX 0.4 UNIT V V V mV/A M
ANALOG OUTPUT
Steady
3
4.0 TIMING DIAGRAM
IOUT ISCP IOCP
1 23
b
6
7
4
5
d
g
8
VC
VVC-EXT
a
VOVLO
Vin
NL 26 V
c
e
Vout
TM
VTM-amb
PC
5V 3V
f
a: VC slew rate (dVC/dt) b: Minimum VC pulse rate (see section 5) c: TOVLO d: TOCP e: PC disable time (TPC-dis) f: VC to PC delay g: TSCP
1. Initiated VC pulse 2. Controller start 3. VIN ramp up 4. VIN = VOVLO 5. VIN ramp down no VC pulse 6. Overcurrent 7. Start up on short circuit 8. PC driven low
Caution:
The module is not designed to start in this sequence. Notes: - Timing and voltage is not to scale - Error pulse width is load dependent
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 4 of 18
VIV0005TFJ
5.0 APPLICATION CHARACTERISTICS
PRELIMINARY DATASHEET
The following values, typical of an application environment, are collected at TJ = 25C unless otherwise noted. See associated figures for general trend data.
ATTRIBUTE No Load Power Dissipation Efficiency (Ambient) Efficiency (Hot) Output Resistance (Ambient) Output Resistance (Hot) Output Resistance (Cold) Output Voltage Ripple VOUT Transient (Positive) VOUT Transient (Negative) SYMBOL PNL AMB HOT ROUT_AMB ROUT_HOT ROUT_COLD VOUT_PP VOUT_TRAN+ VOUT_TRANCONDITIONS / NOTES VIN = 42 V, PC enabled VIN = 42 V, IOUT = 130 A VIN = 42 V, IOUT = 130 A VIN = 42 V VIN = 42 V VIN = 42 V COUT = 0 F, IOUT = 130 A, VIN = 40 V, 20 MHz BW, Section 12 IOUT_STEP = 0 A TO 150A, VIN = 40 V, ISLEW >10 A /us IOUT_STEP = 150 A to 0 A, VIN = 40 V ISLEW > 10 A /us TYP 3.2 89.5 88 0.69 0.85 0.6 116 90 100 UNIT W % % m m m mV mV mV
No Load Power Dissipation vs. Line Voltage
7.5 94 92
130 A Load Efficiency vs. TCASE
Power Dissipation (W)
7.0 6.5
Efficiency (%)
26 29 32 36 39 42 45 49 52 55
6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0
90 88 86 84 82 80 78 -40 -20 VIN : 0 26 V 20 40 42 V 60 55 V 80 100
Input Voltage (V)
TCASE: -40C 25C 100C
Case Temperature (C)
Figure 1 - No load power dissipation vs. VIN
Figure 2 - Full load efficiency vs. temperature
Efficiency & Power Dissipation -40C Case
94 94
Efficiency & Power Dissipation 25C Case
Power Dissipation (W) Power Dissipation (W)
90
90
Efficiency (%)
Efficiency (%)
86 82 78 74 70 66 0 30 26 V 42 V 60 55 V 90 26 V 120 42 V 24 20 16 12 8 4 0 150
86 82 78 74 70 66 0 30 26 V 42 V 60 55 V 90 26 V 120 42 V 24 20 16 12 8 4 0 150
PD
PD
Load Current (A)
VIN: 55 V VIN:
Load Current (A)
55 V
Figure 3 - Efficiency and power dissipation at -40C
Figure 4 - Efficiency and power dissipation at 25C
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 5 of 18
VIV0005TFJ
Efficiency & Power Dissipation 100C Case
94 90
PRELIMINARY DATASHEET
ROUT vs. TCASE at VIN = 42 V
Power Dissipation (W)
0.85 0.80
Efficiency (%)
86 82 78 74 70 66 0 26 52 78 104 24 20 16 12 8 4 0 130
ROUT (m)
0.75 0.70 0.65 0.60 0.55 -40 -20 0 20 40 60 80 100
PD
Load Current (A)
VIN: 26 V 42 V 55 V 26 V 42 V 55 V
I OUT :
Case Temperature (C)
13 A 65 A 130 A
Figure 5 - Efficiency and power dissipation at 100C
Figure 6 - ROUT vs. temperature
Output Voltage Ripple vs. Load
150 130
VRIPPLE (mV PK-PK)
110 90 70 50 30 10 13 26 39 52 65 78 91 104 117 130
Load Current (A)
VIN: 26 V 40 V 55 V
Figure 7 - Full load ripple, 100 F CIN; No external COUT. Board mounted module, scope setting : 20 MHz analog BW, digital filter 1.5 bits -3 dB @ 12 MHz
Figure 8 - VRIPPLE vs. IOUT ; VIN, No external COUT. Board mounted module, scope setting : 20 MHz analog BW, digital filter 1.5 bits -3 dB @ 12 MHz
220 200
Safe Operating Area
160
Limited by Power <10 ms , 195 A Maximum Current
Maximum Load Current vs. TCASE
155 150 145 140 135 130 125 120 115 110
Output Current (A)
< 30C TCASE 150 A Maximum Current Limited by ROUT
100 80 60 40 20 0 0.0 0.2
130 A Maximum Current
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
IOUT_MAX (A)
180 160 140 120
-40
-20
0
20
40
60
80
100
Output Voltage (V)
Case Temperature (C)
Figure 9 - Safe operating area
Figure 10 - Maximum load current using Iout_max = - (2/7) * Tc + 159. Junction temperature less than 125C
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VIV0005TFJ
IM Voltage vs. Load at VIN = 42 V
2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 13 26 TCASE : 39 52 -40C 65 78 25C 91 104 100C 117 130
2.25 2.00 1.75 1.50
PRELIMINARY DATASHEET
IM Voltage vs. Load 25C Case
IM (V)
IM (V)
1.25 1.00 0.75 0.50 0.25 0.00 13 26 39 52 65 78 91 104 117 130
Load Current (A)
VIN:
Load Current (A)
26 V 42 V 55 V
Figure 11 - IM voltage vs. load
Figure 12 - IM voltage vs. load
IM Voltage at 130 A Load vs. TCASE
2.50
2.25
IM (V)
2.00
1.75
1.50 -40 -20 0 20 40 60 80 100
Case Temperature (C)
VIN: 26 V 42 V 55 V
Figure 13 - Full load IM voltage vs. TCASE
Figure 14 - Start up from application of VIN: VC pre-applied
Figure 15 - 0 A- 150 A transient response: CIN = 100 F, no external COUT
Figure 16 - 150 A - 0 A transient response: CIN = 100 F, no external COUT
Rev. 1.1 7/2009
Page 7 of 18
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
VIV0005TFJ
6.0 GENERAL CHARACTERISTICS
PRELIMINARY DATASHEET
Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40C < TJ < 125C (T-Grade); All Other specifications are at TJ = 25C unless otherwise noted.
ATTRIBUTE MECHANICAL Length Width Height Volume Weight Lead Finish SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
L W H Vol W
32.25 / 1.27 21.75 / 0.86 6.48 / 0.255 No heat sink Nickel Palladium Gold 0.51 0.02 0.003
32.5 / 1.28 22.0 / 0.87 6.73 / 0.265 4.82 / 0.29 0.512 / 14.5
32.75 / 1.29 22.25 / 0.88 6.98 / 0.275
mm/in mm/in mm/in cm3/in3 oz/g m
2.03 0.15 0.051
THERMAL Operating Temperature Thermal Capacity ASSEMBLY Peak Compressive Force Applied to Case (Z-axis) Storage Temperature Moisture Sensitivity Level ESD Withstand
TJ
-40 9
125
C Ws/C
Supported by J-lead only TST MSL ESDHBM ESDCDM -40 5 1000 400
5
6 125
lbs C
225C Reflow Human Body Model, "JEDEC JESD 22-A114C.01" Charged Device Model, "JEDEC JESD 22-C101D"
VDC
SOLDERING Peak Temperature During Reflow Peak Time Above 183C Peak Heating Rate During Reflow Peak Cooling Rate Post Reflow SAFETY Working Voltage (IN - OUT) Isolation Voltage (hipot) Isolation Capacitance Isolation Resistance MTBF
1.5 2.5
225 150 2 3
C s C/s C/s
VIN_OUT VHIPOT CIN_OUT RIN_OUT
60 Unpowered Unit MIL HDBK 217 Plus, 25C, Ground Benign Telcordia Issue 2, Method I cTUVus cULus CE Mark RoHS 6 of 6 100 0.018 10 0.02 3.9 6.73 0.022
VDC VDC F M MHrs
Agency Approvals / Standards
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VIV0005TFJ
7.0 USING THE CONTROL SIGNALS VC, PC, TM, IM VTM Control (VC) pin is an input pin which powers the internal VCC circuitry within the specified voltage range of 26 V to 55 V. This voltage is required in order for the VTM to start, and must be applied as long as the input is below 26 V. In order to ensure a proper start, the slew rate of the applied voltage must be within the specified range. VC must be applied first to activate the controller prior to the input. When the input voltage is applied, the VTM output voltage will track the input allowing for a soft-start. If the VC voltage is removed prior to the input reaching 26 V, the VTM may shut down. Some additional notes on using the VC pin: * In most applications, the VTM will be powered by an upstream PRM, in which case the PRM will provide a typical 10 ms VC pulse during startup. In these applications the VC pins of the PRM and VTM should be tied together. * The fault response of the VTM is latching. A positive edge on VC, or toggling PC if VC is continuously applied, is required in order to restart the unit. * The VTM is designed for continuous operation with VC applied. Primary Control (PC) pin can be used to accomplish the following functions: * Delayed start: Upon the application of VC, the PC pin will source a constant 100 A current to the internal RC network. Adding an external capacitor will allow further delay in reaching the 2.5 V threshold for module start. * Auxiliary voltage source: Once enabled in regular operational conditions (no fault), each VTM PC provides a regulated 5 V, 2 mA voltage source. * Output disable: PC pin can be actively pulled down in order to disable the module. Pull down impedance shall be lower than 850 . * Fault detection flag: The PC 5 V voltage source is internally turned off as soon as a fault is detected. It is important to notice that PC doesn't have current sink capability. Therefore, in an array, PC line will not be capable of disabling neighboring modules if a fault is detected. * Fault reset: PC may be toggled to restart the unit if VC is continuously applied.
PRELIMINARY DATASHEET
Temperature Monitor (TM) pin provides a voltage proportional to the absolute temperature of the converter control IC. It can be used to accomplish the following functions: * Monitor the control IC temperature: The temperature in Kelvin is equal to the voltage on the TM pin scaled by 100. (i.e. 3.0 V = 300 K = 27C). If a heat sink is applied, TM can be used to thermally protect the system. * Fault detection flag: The TM voltage source is internally turned off as soon as a fault is detected. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of TM signal. Current Monitor (IM) pin provides a voltage proportional to the output current of the VTM. The voltage will vary between 0.206 V and 1.825 V over the output current range of the VTM (See Figures 11-13). The accuracy of the IM pin will be within 25% under all line and temperature conditions between 50% and 100% load. The accuracy of the pin can be improved using a predictive algorithm based on the input voltage and internal temperature. 8.0 THERMAL CONSIDERATIONS V* I Chip products are multi-chip modules whose temperature distribution varies greatly for each part number as well as with the input / output conditions, thermal management and environmental conditions. Maintaining the top of the VIV0005TFJ case to less than 100C will keep all junctions within the V* I Chip below 125C for most applications. The percent of total heat dissipated through the top surface versus through the J-lead is entirely dependent on the particular mechanical and thermal environment. The heat dissipated through the top surface is typically 60%. The heat dissipated through the J-lead onto the PCB board surface is typically 40%. Use 100% top surface dissipation when designing for a conservative cooling solution. It is not recommended to use a V* I Chip for an extended period of time at full load without proper heatsinking. 9.0 FUSE SELECTION In order to provide flexibility in configuring power systems V* I Chip products are not internally fused. Input line fusing of V* I Chip products is recommended at system level to provide thermal protection in case of catastrophic failure. The fuse shall be selected by closely matching system requirements with the following characteristics: * Current rating (usually greater than maximum VTM current) * Maximum voltage rating (usually greater than the maximum possible input voltage) * Ambient temperature * Nominal melting I2t
Rev. 1.1 7/2009
Page 9 of 18
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
+VIN Synchronous Rectification -VOUT C1 Q1 Enable Primary Gate Drive Q4 +VOUT Cr Lr COUT C2 Power Transformer Q3 18 V -VOUT Right J-lead Gate Drive Supply Primary Stage & Resonant Tank COUT +VOUT Left J-lead
10.0 VTM BLOCK DIAGRAM
v i c o r p o w e r. c o m
Q2 10.5 V Modulator Enable Single Ended Primary Current Sensing Secondary Gate Drive Adaptive Soft Start VIN VREF
OVLO UVLO
CIN
Regulator Supply
VC
-VIN
PC Pull-Up & Source
100 A
3 VMAX 240 AMAX
IM
2.5 V 1.5 K 5V 2 mA Overcurrent Protection Enable Fault Logic
VIV0005TFJ
Fast Current Limit VREF
Slow Current Limit
Over Temperature Protection Enable
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Temperature Dependent Voltage Source 1K 150 K 40 K 2.5 V VREF (127C) 0.01 F
PC
TM
1000 pF
PRELIMINARY DATASHEET
Page 10 of 18
Rev. 1.1 7/2009
VIV0005TFJ
11.0 SINE AMPLITUDE CONVERTER POINT OF LOAD CONVERSION The Sine Amplitude Converter (SAC) uses a high frequency resonant tank to move energy from input to output. The resonant tank formed by Cr and leakage inductance Lr in the power transformer windings as shown in the VTM Block Diagram (See Section 10). The resonant LC tank, operated at high frequency, is amplitude modulated as function of input
PRELIMINARY DATASHEET
voltage and output current. A small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionality and is key to achieving power density. The VIV0005TFJ SAC can be simplified into the following model:
78 pH
LIN == 5 nH LIN 3.7 nH
IOUT IOUT
ROUT ROUT 0.668 m
LOUT = 150 pH
+
RCIN RCIN 6.63 m
VIN VIN CIN CIN 1/40 * IOUT 885 nF IQ IQ 0.08 A
V*I
62 m
RCOUT RCOUT 65
+
+ -
K
+ -
1/40 * VIN
COUT COUT
360 F VOUT VOUT
-
Figure 17 - V*I Chip AC model
-
At no load: VOUT = VIN * K K represents the "turns ratio" of the SAC. Rearranging Eq (1): (1)
IQ = 0 A, Eq. (3) now becomes Eq. (2) and is essentially load independent. A resistor R is now placed in series with VIN as shown in Figure 18.
R
V K = OUT VIN In the presence of load, VOUT is represented by: VOUT = VIN * K - IOUT * ROUT and IOUT is represented by: IOUT = IIN - IQ K
(2)
VIN Vin
+ -
SAC SAC K = 1/32 K = 1/32
Vout VOUT
(3)
Figure 18 - K = 1/32 Sine Amplitude Converter with series input resistor
The relationship between VIN and VOUT becomes: (4) VOUT = (VIN - IIN * R) * K Substituting the simplified version of Eq. (4) (IQ is assumed = 0 A) into Eq. (5) yields: VOUT = VIN * K - IOUT * R * K2 (6) (5)
ROUT represents the impedance of the SAC, and is a function of the RDSON of the input MOSFETs and the winding resistance of the Power transformer. IQ represents the quiescent current of the SAC control and gate drive circuitry. The use of DC voltage transformation provides additional interesting attributes. Assuming for the moment that ROUT and
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Page 11 of 18
VIV0005TFJ
This is similar in form to Eq. (3), where ROUT is used to represent the characteristic impedance of the SAC. However, in this case a real R on the input side of the SAC is effectively scaled by K2 with respect to the output. Assuming that R = 1 , the effective R as seen from the secondary side is 0.98 m, with K = 1/32 as shown in Figure 18. A similar exercise should be performed with the additon of a capacitor, or shunt impedance, at the input to the SAC. A switch in series with VIN is added to the circuit. This is depicted in Figure 19.
PRELIMINARY DATASHEET
S
VIN Vin
+ -
C
SAC SAC K = 1/32 K = 1/32
VVout OUT
Figure 19 - Sine Amplitude Converter with input capacitor
A change in VIN with the switch closed would result in a change in capacitor current according to the following equation: IC(t) = C dVIN dt (7)
Low impedance is a key requirement for powering a high current, low voltage load efficiently. A switching regulation stage should have minimal impedance, while simultaneously providing appropriate filtering for any switched current. The use of a SAC between the regulation stage and the point of load provides a dual benefit, scaling down series impedance leading back to the source and scaling up shunt capacitance (or energy storage) as a function of its K factor squared. However, these benefits are not useful if the series impedance of the SAC is too high. The impedance of the SAC must be low well beyond the crossover frequency of the system. A solution for keeping the impedance of the SAC low involves switching at a high frequency. This enables magnetic components to be small since magnetizing currents remain low. Small magnetics mean small path lengths for turns. Use of low loss core material at high frequencies reduces core losses as well. The two main terms of power loss in the VTM module are: - No load power dissipation (PNL): defined as the power used to power up the module with an enabled power train at no load. - Resistive loss (ROUT): refers to the power loss across the VTM modeled as pure resistive impedance. PDISSIPATED = PNL + PROUT Therefore, POUT = PIN - PDISSIPATED = PIN - PNL - PROUT (11) (10)
Assume that with the capacitor charged to VIN, the switch is opened and the capacitor is discharged through the idealized SAC. In this case, IC = IOUT * K Substituting Eq. (1) and (8) into Eq. (7) reveals: IOUT = C K2
*
The above relations can be combined to calculate the overall module efficiency: = POUT = PIN - PNL - PROUT PIN PIN (12)
(8)
dVOUT dt
(9)
=
VIN * IIN - PNL - (IOUT)2 * ROUT VIN * IIN
Writing the equation in terms of the output has yielded a K2 scaling factor for C, this time in the denominator of the equation. For a K factor less than unity, this results in an effectively larger capacitance on the output when expressed in terms of the input. With a K=1/32 as shown in Figure 19, C=1 F would effectively appear as C=1024 F when viewed from the output.
= 1-
(
PNL + (IOUT)2 * ROUT VIN * IIN
)
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 12 of 18
VIV0005TFJ
12.0 INPUT AND OUTPUT FILTER DESIGN A major advantage of a SAC system versus a conventional PWM converter is that the former does not require large functional filters. The resonant LC tank, operated at extreme high frequency, is amplitude modulated as a function of input voltage and output current and efficiently transfers charge through the isolation transformer. A small amount of capacitance embedded in the input and output stages of the module is sufficient for full functionality and is key to achieving high power density. This paradigm shift requires system design to carefully evaluate external filters in order to: 1.Guarantee low source impedance. To take full advantage of the VTM dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. The connection of the V*I Chip to its power source should be implemented with minimal distribution inductance. If the interconnect inductance exceeds 100 nH, the input should be bypassed with a RC damper to retain low source impedance and stable operation. A single electrolytic or equivalent low-Q capacitor may be used in place of the series RC bypass. 2.Further reduce input and/or output voltage ripple without sacrificing dynamic response. Given the wide bandwidth of the VTM, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the VTM multiplied by its K factor. 3.Protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures. The V*I Chip input/output voltage ranges shall not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it. A criterion for protection is the maximum amount of energy that the input or output switches can tolerate if avalanched.
PRELIMINARY DATASHEET
13.0 CAPACITIVE FILTERING CONSIDERATIONS FOR A SINE AMPLITUDE CONVERTER It is important to consider the impact of adding input and output capacitance to a Sine Amplitude Converter on the system as a whole. Both the capacitance value, and the effective impedance of the capacitor must be considered. A Sine Amplitude Converter has a DC ROUT value which has already been discussed in section 11. The AC ROUT of the SAC contains several terms: * Resonant tank impedance * Input lead inductance and internal capacitance * Output lead inductance and internal capacitance The values of these terms are shown in the behavioral model in section 11. It is important to note on which side of the transformer these impedances appear and how they reflect across the transformer given the K factor. The overall AC impedance varies from model to model but for most models it is dominated by DC ROUT value from DC to beyond 500 KHz. The behavioral model in section 11 should be used to approximate the AC impedance of the specific model. Any capacitors placed at the output of the VTM reflect back to the input of the VTM by the square of the K factor (Eq. 9) with the impedance of the VTM appearing in series. It is very important to keep this in mind when using a PRM to power the VTM. Most PRMs have a limit on the maximum amount of capacitance that can be applied to the output. This capacitance includes both the PRM output capacitance and the VTM output capacitance reflected back to the input. In PRM remote sense applications, it is important to consider the reflected value of VTM output capacitance when designing and compensating the PRM control loop. Capacitance placed at the input of the VTM appear to the load reflected by the K factor, with the impedance of the VTM in series. In step-down VTM ratios, the effective capacitance is increased by the K factor. The effective ESR of the capacitor is decreased by the square of the K factor, but the impedance of the VTM appears in series. Still, in most step-down VTMs an electrolytic capacitor placed at the input of the VTM will have a lower effective impedance compared to an electrolytic capacitor placed at the output. This is important to consider when placing capacitors at the output of the VTM. Even though the capacitor may be placed at the output, the majority of the AC current will be sourced from the lower impedance, which in most cases will be the VTM. This should be studied carefully in any system design using a VTM. In most cases, it should be clear that electrolytic output capacitors are not necessary to design a stable, well-bypassed system.
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 13 of 18
VIV0005TFJ
14.0 CURRENT SHARING The SAC topology bases its performance on efficient transfer of energy through a transformer without the need of closed loop control. For this reason, the transfer characteristic can be approximated by an ideal transformer with some resistive drop and positive temperature coefficient. This type of characteristic is close to the impedance characteristic of a DC power distribution system, both in behavior (AC dynamic) and absolute value (DC dynamic). When connected in an array with the same K factor, the VTM module will inherently share the load current with parallel units, according to the equivalent impedance divider that the system implements from the power source to the point of load. It is important to notice that, when successfully started, VTMs are capable of bi-directional operation. Reverse power transfer is enabled if the VTM input falls within its operating range and the VTM is otherwise enabled. In parallel arrays, because of ROUT, circulating currents are never experienced due to energy conservation law. Some general recommendations to achieve matched array impedances: * Dedicate common copper planes within the PCB to deliver and return the current to the modules. * Provide the PCB layout as symmetric as possible. * Apply same input / output filters (if present) to each unit. For further details see AN:016 Using BCMTM Bus Converters in High Power Arrays.
PRELIMINARY DATASHEET
15.0 REVERSE INRUSH CURRENT PROTECTION The VIV0005TFJ provides reverse inrush protection which prevents reverse current flow until the input voltage is high enough to first establish current flow in the forward direction. In the event that there is a DC voltage present on the output before the VTM is powered up, this feature protects sensitive loads from excessive dV/dT during power up as shown in Figure 21. If a voltage is present at the output of the VTM which satisfies the condition VOUT > VIN * K after a successful power up the energy will be transferred from secondary to primary. The input to output ratio of the VTM will be maintained. The VTM will continue to operate in reverse as long as the input and output voltages are within the specified range. The VIV0005TFJ has not been qualified for continuous reverse operation.
PC VC IM TM
R
R
VTM
VIN
+In +Out
+ _
-In -Out
Supply
A VC
B
CD
E
F
G
H
VIN
Supply
VIN
VIN
ZIN_EQ1
VTM1
RO_1
ZOUT_EQ1
VOUT
VOUT
VOUT
Supply
ZIN_EQ2
+ -
VTM2
RO_2
ZOUT_EQ2
TM
Load
DC
PC
A: VOUT supply > 0 V
ZIN_EQn
VTMn
RO_n
ZOUT_EQn
B: VC to -IN > 11.5 V controller wakes-up, PC & TM pulled high, reverse inrush protection blocks VOUT supplying VIN C: VIN supply ramps up D: VIN > VOUT/K, powertrain starts in normal mode E: VIN supply ramps down F: VIN > VOUT/K, powertrain transfers reverse energy G: VOUT ramps down, VIN follows H: VC turns off
Figure 20 - VTM array
Figure 21 - Reverse inrush protection
Rev. 1.1 7/2009
Page 14 of 18
v i c o r p o w e r. c o m
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
VIV0005TFJ
16.0 LAYOUT CONSIDERATIONS The VIV0005TFJ requires equal current density along the output J-leads to achieve rated efficiency and output power level. The negative output J-leads are not connected internally and must be connected on the board as close to the VTM as possible. The layout must also prevent the high output current of the VIV0005TFJ from interfering with the input-referenced signals. To achieve these requirements, the following layout guidelines are recommended: * The total current path length from any point on the V+OUT J-leads to the corresponding point on the V-OUT J-leads should be equal (see Figure 22) .
PRELIMINARY DATASHEET
Figure 22 - Equal current path
* Use vias along the negative output J-leads to connect the negative output to a common power plane. * Use sufficient copper weight and number of layers to carry the output current to the load or to the output connectors. * Be sure to include enough vias along both the positive and negative J leads to distribute the current among the layers of the PCB. * Do not run input-referenced signal traces (VC, PC, TM and IM) between the layers of the secondary outputs. * Run the input-referenced signal traces (VC, PC, TM and IM) such that V-IN shields the signals. See AN:005 FPA Printed Circuit Board Layout Guidelines for more details. Equalizing the current paths is most easily accomplished by centering the VTM output J-leads between the output connections of the PCB and by designing the board such that the layout is symmetric from both sides of the output and from the front and back ends of the output as shown in Figures 23 and 24.
Figure 23 - Symmetric layout
Figure 24 - Symmetric layout
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 15 of 18
VIV0005TFJ
17.0 MECHANICAL DRAWING
PRELIMINARY DATASHEET
17.1 RECOMMENDED LAND PATTERN
4 A B C D E F G H J K L
3
2
1
M
N
Bottom View
NOTES: mm 1. DIMENSIONS ARE inch . 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: X.XX = 0.25 [0.01] X.XXX = 0.127 [0.005] 3. RoHS COMPLIANT PER CST-0001 LATEST REVISION. DXF and PDF files are available on vicorpower.com
Signal Name +In -In IM TM VC PC +Out -Out
Designation M2, M1 M4, M3 N3 N4 N2 N1 A3-L3, A2-L2 A4-L4, A1-L1
Click here to view original mechanical drawing on the Vicor website.
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 16 of 18
VIV0005TFJ
17.2 RECOMMENDED LAND PATTERN FOR PUSH PIN HEAT SINK
PRELIMINARY DATASHEET
RECOMMENDED LAND PATTERN (NO GROUNDING CLIPS)
TOP SIDE SHOWN
36.50 1.437 2.95 0.07 o 0.116 0.003 (2) PL.
NON-PLATED THRU HOLE SEE NOTE 1
( 18.25 ) 0.719
DASHED LINE INDICATES VIC POSITION
7.63 0.300
( 3.50 ) 0.138
NOTES:
( 22.26 ) 0.876
1. MAINTAIN 3.50 [0.138] DIA. KEEP-OUT ZONE FREE OF COPPER, ALL PCB LAYERS. 2. (A) MINIMUM RECOMMENDED PITCH IS 39.50 [1.555], THIS PROVIDES 7.00 [0.275] COMPONENT EDGE-TO-EDGE SPACING, AND 0.50 [0.020] CLEARANCE BETWEEN VICOR HEAT SINKS. (B) MINIMUM RECOMMENDED PITCH IS 41.00 [1.614], THIS PROVIDES 8.50 [0.334] COMPONENT EDGE-TO-EDGE SPACING, AND 2.00 [0.079] CLEARANCE BETWEEN VICOR HEAT SINKS. 3. V*I CHIP LAND PATTERN SHOWN FOR REFERENCE ONLY; ACTUAL LAND PATTERN MAY DIFFER. DIMENSIONS FROM EDGES OF LAND PATTERN TO PUSH-PIN HOLES WILL BE THE SAME FOR ALL FULL SIZE V*ICHIP PRODUCTS. 4. RoHS COMPLIANT PER CST-0001 LATEST REVISION.
7.00 0.276
2.51 0.099
( 31.48 ) 1.239 39.50 1.555 SEE NOTE 2A
RECOMMENDED LAND PATTERN (With GROUNDING CLIPS)
TOP SIDE SHOWN
38.03 1.497 o 2.95 0.07 0.116 0.003 (2) PL.
NON-PLATED THRU HOLE SEE NOTE 1
0.76 0.030 ( 18.25 ) 0.719
36.50 1.437
DASHED LINE INDICATES VIC POSITION
5. UNLESS OTHERWISE SPECIFIED: DIMENSIONS ARE MM [INCH]. TOLERANCES ARE: X.X [X.XX] = 0.3 [0.01] X.XX [X.XXX] = 0.13 [0.005]
0.44 0.017
7.63 0.300
( 3.50 ) 0.138
6. PLATED THROUGH HOLES FOR GROUNDING CLIPS (33855) SHOWN FOR REFERENCE. HEATSINK ORIENTATION AND DEVICE PITCH WILL DICTATE FINAL GROUNDING SOLUTION.
6.12 0.241
( 22.26 ) 0.876
7.00 0.276
o 2.03 0.080 (2) PL.
PLATED THRU HOLE SEE NOTE 6
2.51 0.099
( 31.48 ) 1.239 41.00 1.614 SEE NOTE 2B
Click here to view original mechanical drawing on the Vicor website.
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 17 of 18
VIV0005TFJ
PRELIMINARY DATASHEET
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgement. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages.
Vicor's comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor's Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965.
Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com
V*I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
v i c o r p o w e r. c o m
Rev. 1.1 7/2009
Page 18 of 18

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